The invention concerns an arrangement for synchronizing the handling of asynchronously occurring requests for program interruption in a data processing system.
For the implementation of program interrupts and the control of priority-dependent program level switching, known data processing systems employ essentially two principles:
1. the periodic testing of asynchronous processes external to the processor for operator intervention, if necessary, and
2. the direct intervention of the asynchronous external processes in the processor sequence (subject to control by masks and priority conventions).
The first principle is used mainly in processors with only one program level (i.e., with only one instruction address register, only one condition code register, and only one local storage), so that, if necessary, i.e., in the case of an asynchronous, external request, a switch may be effected to the programs provided for external operation.
In contrast to this, processors operating in accordance with the second principle are subject to particular conditions inherent in their circuit structure:
priority circuits for determining in each case the highest request priority when several requests are simultaneously encountered, and PA1 separate instruction address registers, condition code registers, and local storages associated with the individual priority levels.
The following description is based on a processor operating in accordance with the second principle. This processor is assumed to have eight interrupt levels with the appertaining instruction address registers, condition code registers, and local storages. These eight interrupt levels are designated as 0 to 7, the highest priority being assigned to level 0 and the lowest to level 7.
For controlling the eight interrupt levels or, as will be described further on, program levels, the processor is provided with the necessary priority circuits as well as with different masks to overrule the control of the priority circuits within defined limits.
In known data processing systems of this kind the eight program levels are associated with respective microprograms provided for implementing the associated processes. FIG. 3 in the drawings described below shows which functions can be associated with the individual program levels if the processor essentially serves to fulfill service tasks. Such a service processor generally is in charge of the tasks of initial program loading, error detection and diagnosis, operating particular system components, such as a console with keyboard and display units, and, in the case of more sophisticated data processing systems, of system restructuring. The aforementioned tasks which such service processors have to fulfill are by no means exhaustive but are merely an excerpt from a catalogue of tasks that can be entrusted to service processors.
In the example of FIG. 3 the program level 0 with the highest priority accommodates all microprograms for analyzing and handling processor errors (EA) detected by error check circuits.
The program level 1 which can be activated by errors (PSF) in the internal power supply serves to switch off the different internal power supply units, following a particular sequence.
Program level 2 accommodates the microprogram associated with a remote service terminal (RS), by means of which a service processor arranged in a service station can be connected for remote service purposes, via modems or similar communication adaptors, to corresponding other processors which can be linked thereby in a star configuration to a central service processor.
Program level 3 contains, for example, microprograms for operating the keyboard and display (DISPL) of a processor console.
Program level 4 contains the microprograms of a bus adaptor (BBA), via which the service processor is connectable to other parts of an associated processing system.
The microprogram for operating, for example, a diskette (DISK) for collecting error data for diagnostic and maintenance purposes is on program level 5, as shown in FIG. 3.
The microprograms for testing the system status (SYST) and for measuring the internal operating voltages occupy program level 6.
Finally, all transient microprograms (TRANS) are accommodated on the lowest level 7.
The various processes, which are mentioned here only briefly, can operate in parallel, i.e., asynchronously, so that their requests to the associated microprograms can become active asynchronously in respect to the microprogram currently being executed.
A request with highest priority is entitled to interrupt a currently executing program of lower priority between the execution of one micro instruction and the retrieval of the next sequential micro instruction. The address of the next micro instruction and the last valid condition code as well as the full appertaining local storage contents are preserved until the interrupted program is resumed.
Generally, this means that as new external, asynchronous requests occur, or after a program level has been serviced, a renewed priority check must be made to determine which currently active request thas the highest priority, so that the request concerned can be assigned control of the processor.
Thus, the microprograms executing on the different program levels can competitively acquire control of the processor. This method which is generally employed for processors operating according to the second principle, i.e., interruption driven processors, has three serious disadvantages:
It is highly susceptible to faults and defects, since faulty asynchronous requests which may be caused by faulty circuits may cause displacement of current programs in accordance with their priority, and produce secondary effects by erroneously called programs.
A "stationary state" is difficult to predict or cannot be predicted at all, so that this method leads to unforeseeable "overflows".
Errors caused by circuits or microprograms are very difficult to analyze in this "uncontrolled" arrangement and require a considerable amount of time.
The object of this invention is to eliminate the foregoing disadvantages. External requests are not permitted to cause asynchronous interruptions. In the case of accepted interruptions (program changes) only particular control blocks and not the microprograms proper are changed. In addition, the control blocks associated with a higher level program language are organized to determine the instruction types and storage areas permissible for the respective program level.
In accordance with the invention, this problem is solved by means of the features described and claimed herein.
Other advantages, embodiments, developments and features of the subject matter of this invention may be understood from the description and claims.
By means of the invention essentially two advantages are obtained:
1. External interruption requests such as requests by input/output units, which conventionally would be accepted on an asynchronous basis, may be masked out of contention during the execution of other programs.
2. The switching of the control blocks associated with the passage of control between individual program levels may be effected synchronously at a particular predetermined stage in the interpretation phase of an instruction in the program which is to be interrupted.